In recent years, there has been a demand on reading and writing data at a high speed from and into semiconductor memory devices, such as dynamic RAM. Synchronous dynamic RAM that can read and write data in synchronization with an external clock signal has been developed to meet the aforementioned demand. In such synchronous dynamic RAM, a command is input based on a logical combination of signals, such as CS (chip select), RAS (row address strobe), CAS (column address strobe), WE (write enable), etc. In an operation mode corresponding to the command, data are read or written in synchronization with an external clock signal.
As described above, a synchronous dynamic RAM reads and writes data in synchronization with an external clock. As the frequency of the clock signal increases, e.g. to 125 MHz, 133 MHz, or 143 MHz, the operating speed of the internal circuit of the synchronous dynamic RAM must also increase in step with this increase in clock frequency. For example, when the frequency of the external clock signal is 125 MHz, data must be read or written consecutively every 8 ns (nanosecond) in burst mode. When the frequency of the external clock signal is 133 MHz data must be read or written consecutively every 7.5 ns in burst mode. When the frequency of the external clock is 143 MHz, data must be read or written consecutively every 7 ns in burst mode.
The objective of the present invention is to provide a semiconductor memory device that can read and write data at a high speed.